1. Field of the Invention
The present invention relates to the technology of memory module. More particularly, the present invention relates to a memory refresh circuit and a memory refresh method.
2. Description of the Related Art
A memory cell of a DRAM memory conventionally is composed of a transistor and a capacitor. Because the information is stored in the memory cell by charging the capacitor, the occurrence of a current leakage through the capacitor can negatively delete the stored information. In order to keep the stored information present in the memory cell, a conventional xe2x80x9crefreshxe2x80x9d operation thus is performed.
Referring to FIG. 1, a block diagram schematically illustrates a conventional memory refresh circuit. Each block memory 14a, 14b, 14c, etc. is respectively connected to a corresponding word line driver (12a, 12b, 12c, etc.) and a decoder block (10a, 10b, 10c, etc). A row address counter 16 generates and transmits a row address to the decoder blocks (10a, 10b, 10c, etc.). A row address strobe monitor or timer (TRAS) 18 is connected to the row address counter 16 and to the block memories (14a, 14b, 14c, etc.). The memory refresh operation is commanded by the delivery of a Column address strobe Before Row address strobe (CBR) memory refresh signal to the TRAS monitor 18. The TRAS monitor 18 then checks whether the refresh of all the block memories (14a, 14b, 14c, etc.) is completed before performing the next refresh operation. As a result, only a single CBR refresh operation can be performed within a memory refresh cycle.
Referring to FIG. 2, a time/sequence diagram illustrates a conventional memory refresh operation. At the time cycle T1, a memory refresh command is triggered by the activation of a CMD signal while the activation of the address signal XADD delivers the address XADD0 to be refreshed. A CBR refresh of the address XADD0 then starts. Once the refresh of the address XADD0 of all the block memories (14a, 14b, 14c, etc.) is completed, an activation of the CMD signal at the time cycle T7 commands another refresh operation with respect to another address XADD1.
With the above method, only a single CBR refresh operation thus can be performed within a memory refresh cycle. Moreover, while the size of the DRAM memory is increased, the retention time, on the contrary, cannot be unlimitedly increased. As a result, if more bits have to be refreshed within a fixed cycle as conventionally done, the repetitive sudden peaks of refresh currents can damage the power supply system.
A major aspect of the present invention is to provide a memory refresh circuit and a memory refresh method in which at least two refresh operations are performed within the same refresh cycle.
Another aspect of the present invention is to provide a memory refresh circuit and a memory refresh method in which the refresh current is better distributed during a time such that the failure of the power supply system can be prevented.
Another aspect of the present invention is to provide a memory refresh circuit and a memory refresh method in which the time necessary for a memory CBR refresh operation is reduced such that the utility rate of the memory is increased.
To attain the foregoing and other objectives, the present invention, according to a preferred embodiment, provides a memory refresh circuit that is connected to a plurality of block memories, each of the block memories being respectively connected to a word line driver. According to a preferred embodiment of the present invention, the memory refresh circuit comprises: a plurality of row address latches and a plurality of row address strobe monitors, each of the row address latches and one of the row address strobe monitors being connected to each other and to one of the block memories; and a row address counter connected to the row address latches to transmit a plurality of different addresses to the row address latches.
To attain the foregoing and other objectives, the present invention, according to another preferred embodiment, provides a memory refresh circuit that comprises: a memory array comprised of a plurality of block memories; a plurality of word line drivers respectively connected to each of the block memories, each of the word line drivers driving a word line selected in the corresponding block memory; a plurality of row address latches and a plurality of row address strobe monitors, each of the row address latches and one of the row address strobe monitors being both connected to each other and to one of the block memories via one of the word line drivers; and a row address counter connected to the row address latches to transmit a plurality of different addresses to the row address latches.
In the above preferred embodiments, the row address counter delivers successive addresses to each of the row address latches. When a memory refresh signal is transmitted to one of the row address strobe monitor for a specific address, the corresponding row address latch latches the corresponding address to perform the memory refresh operation.
To attain the foregoing and other objectives, the present invention, according to another preferred embodiment, provides a memory refresh method that comprises: generating a first memory refresh signal; generating an address signal; and latching the address signal to perform, according to the first memory refresh signal, a refresh operation to the address corresponding to the address signal while, at the same time, generating a second memory refresh signal, wherein the first and second memory refresh signals are within a same memory refresh cycle.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.